Frequency dividers are generally used, for example, in frequency synthesizers to provide signals in stepped frequencies. One field of application for frequency dividers are, e.g. PLL (Phase Locked Loop) circuits as used in mobile radio technology. In these circuits, a number of communication channels are only a few 100 kHz apart from one another in the GHz band, and the PLL circuit must ideally be capable of generating output frequencies, which are precisely synchronized to these channels. As a rule, a fractional frequency divider is used in the feedback path of the PLL circuits.
Another field of application for frequency dividers is, for example, digital signal processing and microprocessor technology. In the case of signal processing devices, it is often a requirement to clock different modules with different frequencies, which are a few MHz apart from one another (e.g. from 70 MHz to 170 MHz). A register or processor operating, e.g. at a maximum frequency of 152 MHz can only be operated optimally if this exact clock frequency is provided, if possible. If, e.g. only two different frequencies, for instance 120 MHz and 170 MHz, are available, one is forced to operate the processor at 120 MHz, as a result of which 32 MHz of performance are lost. Using a frequency synthesizer, which covers the range between 120 MHz and 170 MHz in 10-MHz steps, the microprocessor can be operated at 150 MHz and only 2 MHz of performance are lost.
These examples show that frequency dividers capable of dividing a predetermined input frequency not only by an integral factor N but also by fractions thereof, namely N+m/k, are required. A method for dividing frequency of a signal is disclosed in U.S. Pat. No. 6,114,915 to Altera Corporation. It includes the steps of (1) applying the signal to down counter (2) storing a first count value and a second count value in memory (3) loading the down counter the first count value (4) detecting when the down counter counts to the end of first count value (5) count value toggling the output signal when the down counter reaches end of count for the first count value (6) loading the down counter with the second count value (7) toggling the output signal when the down counter reaches end of count for the second count value and repeating steps (3) to (6).
The drawback of the aforesaid frequency divider is that it is not possible to obtain a 50% duty cycle at the output if the division factor is an odd number. This can be best understood with an example. Consider a case of divide by three operation. In this case, the memory should be loaded with the bits corresponding to the On Time and Off Time of the divided clock. In order to achieve 50% duty cycle at the output, the load bits corresponding to On Time and Off Time should be 1.5, which is not possible.
What is desired therefore, is a counter that can operate both in a normal division mode and in a fractional division mode.